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1 ? fn8126.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005, 2006. all rights reserved all other trademarks mentioned are the property of their respective owners. x5043, x5045 4k, 512 x 8 bit cpu supervisor with 4k spi eeprom these devices combine four popular functions, power-on reset control, watchdog timer, supply voltage supervision, and block lock protect serial eeprom memory in one package. this combination lo wers system cost, reduces board space requirements, and increases reliability. applying power to the device activates the power-on reset circuit which holds reset /reset active for a period of time. this allows the power supply and oscillator to stabilize before the processor executes code. the watchdog timer provides an independent protection mechanism for microcontrollers. when the microcontroller fails to restart a timer within a selectable time out interval, the device activates the reset /reset signal. the user selects the interval from three preset values. once selected, the interval does not change, even after cycling the power. the device?s low v cc detection circuitry protects the user?s system from low voltage conditions, resetting the system when v cc falls below the minimum v cc trip point. reset /reset is asserted until v cc returns to proper operating level and stabilizes. four industry standard v trip thresholds are available, howev er, intersil?s unique circuits allow the threshold to be r eprogrammed to meet custom requirements or to fine-tune t he threshold for applications requiring higher precision. the memory portion of the device is a cmos serial eeprom array with intersil?s block lock protection. the array is internally organized as 512 x 8. the device features a serial peripheral interface (spi) and software protocol allowing operation on a simple four-wire bus. the device utilizes intersil?s proprietary direct write ? cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. features ?low v cc detection and reset assertion - four standard reset threshold voltages 4.63v, 4.38v, 2.93v, 2.63v - re-program low v cc reset threshold voltage using special programming sequence. - reset signal valid to v cc = 1v ? selectable time out watchdog timer ? long battery life with low power consumption - <50a max standby current, watchdog on - <10a max standby current, watchdog off ? 4kbits of eeprom?1m write cycle endurance ? save critical data with block lock ? memory - protect 1/4, 1/2, all or none of eeprom array ? built-in inadvertent write protection - write enable latch - write protect pin ? spi interface - 3.3mhz clock rate ? minimize programming time - 16-byte page write mode - 5ms write cycle time (typical) ? available packages - 8 ld msop, 8 ld soic, 8 ld pdip - 14 ld tssop ? pb-free plus anneal available (rohs compliant) applications ? communications equipment - routers, hubs, switches - set top boxes ? industrial systems - process control - intelligent instrumentation ? computer systems - desktop computers - network servers ? battery powered equipment data sheet march 16, 2006
2 fn8126.2 march 16, 2006 typical application block diagram uc reset cs sck si so wp vcc vss reset spi vcc vss x5043 2.7-5.0v 10k watchdog timer command decode & control logic si so sck cs /wdi v cc por and low generation v trip + - reset (x5043) voltage reset protect logic 4kbits eeprom watchdog detector wp array status register transition reset reset & watchdog timebase reset (x5045) x5043, x5045 standard v trip level suffix 4.63v (+/-2.5%) -4.5a 4.38v (+/-2.5%) -4.5 2.93v (+/-2.5%) -2.7a 2.63v (+/-2.5%) -2.7 see ?ordering information? on page 3. for more details for custom settings, call intersil. x5043, x5045
3 fn8126.2 march 16, 2006 ordering information part number reset (active low) part marking part number reset (active high) part marking v cc range v trip range temp range (c) package x5043p-4.5a x5043p al x5045p-4.5a x5045p al 4.5-5.5v 4.5-4.75 0 to 70 8 ld pdip x5043pz-4.5a (note) x5043p z al x5045pz-4.5a (note) x5045p z al 0 to 70 8 ld pdip (pb-free) x5043pi-4.5a x5043p am x5045pi-4.5a x5045p am -40 to 85 8 ld pdip x5043piz-4.5a (note) x5043p z am x5045piz-4.5a (note) x5045p z am -40 to 85 8 ld pdip (pb-free) x5043s8-4.5a x5043 al x5045s8-4.5a x5045 al 0 to 70 8 ld soic x5043s8z-4.5a (note) x5043 z al x5045s8z-4.5a (note) x5045 z al 0 to 70 8 ld soic (pb-free) x5043s8i-4.5a* x5043 am x5045s8i-4.5a* x5045 am -40 to 85 8 ld soic x5043s8iz-4.5a* (note) x5043 z am x5045s8iz-4.5a* (note) x5045 z am -40 to 85 8 ld soic (pb-free) x5043m8-4.5a aem x5045m8-4.5a aev 0 to 70 8 ld msop x5043m8z-4.5a (note) dbs x5045m8z-4.5a (note) dcb 0 to 70 8 ld msop (pb-free) x5043m8i-4.5a aen x5045m8i-4.5a aew -40 to 85 8 ld msop x5043m8iz-4.5a (note) dbm x5045m8iz-4.5a (note) dbx -40 to 85 8 ld msop (pb-free) x5043v14i-4.5a x5043v am x5045v14i-4.5a x5045v am -40 to 85 14 ld tssop x5043v14iz-4.5a (note) x5043v z am x5045v14iz-4.5a (note) x5045v z am -40 to 85 14 ld tssop (pb-free) x5043p x5043p x5045p x5045p 4.25-4.5 0 to 70 8 ld pdip x5043pz (note) x5043p z x5045pz (note) x5045p z 0 to 70 8 ld pdip (pb-free) x5043pi x5043p i x5045pi x5045p i -40 to 85 8 ld pdip x5043piz (note) x5043p z i x5045piz (note) x5045p z i -40 to 85 8 ld pdip (pb-free) x5043s8* x5043 x5045s8* x5045 0 to 70 8 ld soic x5043s8z* (note) x5043 z x5045s8z* (note) x5045 z 0 to 70 8 ld soic (pb-free) x5043s8i* x5043 i x5045s8i* x5045 i -40 to 85 8 ld soic x5043s8iz* (note) x5043 z i x5045s8iz* (note) x5045 z i -40 to 85 8 ld soic (pb-free) x5043m8 aeo x5045m8 aex 0 to 70 8 ld msop x5043m8z (note) dbn x5045m8z (note) dby 0 to 70 8 ld msop (pb-free) x5043m8i aep x5045m8i aey -40 to 85 8 ld msop x5043m8iz (note) dbj x5045m8iz (note) dbt -40 to 85 8 ld msop (pb-free) x5043v14i x5043v i x5045v14i x5045v i -40 to 85 14 ld tssop x5043v14iz (note) x5043v z i x5045v14iz (note) x5045v z i -40 to 85 14 ld tssop (pb-free) x5043, x5045
4 fn8126.2 march 16, 2006 x5043p-2.7a x5043p an x5045p-2.7a x5045p an 2.7-5.5v 2.85-3.0 0 to 70 8 ld pdip x5043pz-2.7a (note) x5043p z an x5045pz-2.7a (note) x5045p z an 0 to 70 8 ld pdip (pb-free) x5043pi-2.7a x5043p ap x5045pi-2.7a x5045p ap -40 to 85 8 ld pdip x5043piz-2.7a (note) x5043p z ap x5045piz-2.7a (note) x5045p z ap -40 to 85 8 ld pdip (pb-free) x5043s8-2.7a* x5043 an x5045s8-2.7a x5045 an 0 to 70 8 ld soic x5043s8z-2.7a* (note) x5043 z an x5045s8z-2.7a (note) x5045 z an 0 to 70 8 ld soic (pb-free) x5043s8i-2.7a* x5043 ap x5045s8i-2.7a x5045 ap -40 to 85 8 ld soic x5043s8iz-2.7a* (note) x5043 z ap x5045s8iz-2.7a (note) x5045 z ap -40 to 85 8 ld soic (pb-free) x5043m8-2.7a* aeq x5045m8-2.7a aez 0 to 70 8 ld msop x5043m8z-2.7a (note) dbr x5045m8z-2.7a (note) dca 0 to 70 8 ld msop (pb-free) x5043m8i-2.7a* aer x5045m8i-2.7a afa -40 to 85 8 ld msop x5043m8iz-2.7a* (note) dbl x5045m8iz-2.7a (note) dbw -40 to 85 8 ld msop (pb-free) x5043v14i-2.7a x5043v ap x5045v14i-2.7a x5045v ap -40 to 85 14 ld tssop x5043v14iz-2.7a (note) x5043v z ap x5045v14iz-2.7a (note) x5045v z ap -40 to 85 14 ld tssop (pb-free) x5043p-2.7 x5043p f x5045p-2.7 x5045p f 2.55-2.7 0 to 70 8 ld pdip x5043pz-2.7 (note) x5043p z f x5045pz-2.7 (note) x5045p z f 0 to 70 8 ld pdip (pb-free) x5043pi-2.7 x5043p g x5045pi-2.7 x5045p g -40 to 85 8 ld pdip x5043piz-2.7 (note) x5043p z g x5045piz-2.7 (note) x5045p z g -40 to 85 8 ld pdip (pb-free) x5043s8-2.7* x5043 f x5045s8-2.7* x5045 f 0 to 70 8 ld soic x5043s8z-2.7* (note) x5043 z f x5045s8z-2.7* (note) x5045 z f 0 to 70 8 ld soic (pb-free) x5043s8i-2.7* x5043 g x5045s8i-2.7* x5045 g -40 to 85 8 ld soic x5043s8iz-2.7* (note) x5043 z g x5045s8iz-2.7* (note) x5045 z g -40 to 85 8 ld soic (pb-free) x5043m8-2.7 aes x5045m8-2.7 afb 0 to 70 8 ld msop x5043m8z-2.7 (note) dbp x5045m8z-2.7 (note) dbz 0 to 70 8 ld msop (pb-free) x5043m8i-2.7* aet x5045m8i-2.7 afc -40 to 85 8 ld msop x5043m8iz-2.7* (note) dbk x5045m8iz-2.7 (note) dbu -40 to 85 8 ld msop (pb-free) x5043v14i-2.7 x5043v g x5045v14i-2.7 x5045v g -40 to 85 14 ld tssop x5043v14iz-2.7 (note) x5043v z g x5045v14iz-2.7 (note) x5045v z g -40 to 85 14 ld tssop (pb-free) *add "-t1" suffix for tape and reel. note: intersil pb-free plus anneal products employ special pb-free material sets ; molding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb- free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. ordering information (continued) part number reset (active low) part marking part number reset (active high) part marking v cc range v trip range temp range (c) package x5043, x5045
5 fn8126.2 march 16, 2006 pin configuration pin descriptions serial output (so) so is a push/pull serial data out put pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. serial input (si) si is the serial data input pin. all opcodes, byte addresses, and data to be written to the memory are input on this pin. data is latched by the rising edge of the serial clock. serial clock (sck) the serial clock controls the serial bus timing for data input and output. opcodes, addresses, or data present on the si pin is latched on the rising edge of the clock input, while data on the so pin changes after the falling edge of the clock input. chip select (cs /wdi) when cs is high, the x5043, x5045 are deselected and the so output pin is at high impedance and, unless an internal write operation is underway, th e x5043, x5045 will be in the standby power mode. cs low enables the x5043, x5045, placing it in the active power mode. it should be noted that after power-up, a high to low transition on cs is required prior to the start of any operation. write protect (wp ) when wp is low, nonvolatile writ es to the x5043, x5045 are disabled, but the part other wise functions normally. when wp is held high, all functions, including non volatile writes operate normally. wp going low while cs is still low will interrupt a write to the x5043, x5045. if the internal write cycle has already bee n initiated, wp going low will have no affect on a write. reset (reset , reset) x5043, x5045, reset /reset is an active low/high, open drain output which goes active whenever v cc falls below the minimum v cc sense level. it will remain active until v cc rises above the minimum v cc sense level for 200ms. reset /reset also goes active if the watchdog timer is enabled and cs remains either high or low longer than the watchdog time out period. a falling edge of cs will reset the watchdog timer. principles of operation power-on reset application of power to the x5043, x5045 activate a power- on reset circui t. this circui t pulls the reset /reset pin active. reset /reset prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. when v cc exceeds the device v trip value for 200ms (nominal) the circuit releases reset /reset, allowing the processor to begin executing code. low voltage monitoring during operation, the x5043, x5045 monitor the v cc level and asserts reset /reset if supply voltage falls below a preset minimum v trip . the reset /reset signal prevents the microprocessor from operating in a power fail or brownout condition. the reset /reset signal remains active until the voltage drops below 1v. it also remains active until v cc returns and exceeds v trip for 200ms. watchdog timer the watchdog timer circuit monitors the microprocessor activity by monitoring the wdi input. the microprocessor must toggle the cs /wdi pin periodically to prevent an active reset /reset signal. the cs /wdi pin must be toggled from high to low prior to th e expiration of the watchdog time out period. the state of two nonvolatile control bits in the status register determines the watchdog timer period. the microprocessor can change these watchdog bits. with 8 ld soic/pdip/msop cs /wdi wp so 1 2 3 4 reset /reset 8 7 6 5 v cc x5043, x5045 v ss sck si 14 ld tssop cs nc so 1 2 3 4 reset /reset 14 13 12 11 v cc x5043, x5045 nc nc nc wp nc 5 6 7 v ss nc 10 9 8 sck si pin names symbol description cs /wdi chip select input so serial output si serial input sck serial clock input wp write protect input v ss ground v cc supply voltage reset /reset reset output x5043, x5045
6 fn8126.2 march 16, 2006 no microprocessor action, the watchdog timer control bits remain unchanged, even during total power failure. v cc threshold reset procedure the x5043, x5045 are shipped with a standard v cc threshold (v trip ) voltage. this value will not change over normal operating and storage conditions. however, in applications where the standard v trip is not exactly right, or if higher precision is needed in the v trip value, the x5043, x5045 threshold may be adjusted. the procedure is described below, and uses the application of a high voltage control signal. setting the v trip voltage this procedure is used to set the v trip to a higher voltage value. for example, if the current v trip is 4.4v and the new v trip is 4.6v, this procedure will di rectly make the change. if the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value. to set the new v trip voltage, apply the desired v trip threshold voltage to the v cc pin and tie the wp pin to the programming voltage v p . then send a wren command, followed by a write of data 00h to address 01h. cs going high on the write operation initiates the v trip programming sequence. bring wp low to complete the operation. note: this operation also writes 00h to array address 01h. resetting the v trip voltage this procedure is used to set the v trip to a ?native? voltage level. for example, if the current v trip is 4.4v and the new v trip must be 4.0v, then the v trip must be reset. when v trip is reset, the new v trip is something less than 1.7v. this procedure must be used to set the voltage to a lower value. to reset the v trip voltage, apply at least 3v to the v cc pin and tie the wp pin to the programming voltage v p . then send a wren command, followed by a write of data 00h to address 03h. cs going high on the write operation initiates the v trip programming sequence. bring wp low to complete the operation. note: this operation also writes 00h to array address 03h. 01234567 sck si cs 06h 012345678910 12 13 14 15 8 bits 01h 02h wp v p = 15-18v 00h wren write address data 11 figure 1. set v trip level sequence (v cc = desired v trip value.) x5043, x5045
7 fn8126.2 march 16, 2006 01234567 sck si cs 06h 012345678910 12 13 14 15 8 bits 03h 02h wp v p = 15-18v 00h wren write address data 11 figure 2. reset v trip level sequence (v cc > 3v. wp = 15?18v) 1 2 3 4 8 7 6 5 x5043 v trip adj. v p reset 4.7k si so cs sck c adjust run x5045 figure 3. sample v trip reset circuit x5043, x5045
8 fn8126.2 march 16, 2006 spi serial memory the memory portion of the device is a cmos serial eeprom array with intersil?s block lock protection. the array is internally organized as 512 x 8 bits. the device features a serial peripheral interface (spi) and software protocol allowing operation on a simple four-wire bus. the device utilizes intersil?s proprietary direct write ? cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. the device is designed to interface directly with the synchronous serial peripheral interface (spi) of many popular microcontroller families. the device contains an 8-bit instru ction register that controls the operation of the device. the instruction code is written to the device via the si input. th ere are two write operations that requires only the instruction byte. there are two read operations that use th e instruction byte to initiate the output of data. the remainder of the operations require an instruction byte, an 8-bit address, then data bytes. all instruction, address and data bits are clocked by the sck input. all instructions (table 1), addresses and data are transferred msb first. clock and data timing data input on the si line is latched on the first rising edge of sck after cs goes low. data is output on the so line by the falling edge of sck. sck is static, allowing the user to stop the clock and then start it again to resume operations where left off. cs must be low during the entire operation. note: *instructions are shown msb in leftmost pos ition. instructions are transferred msb first. v trip programming apply 5v to v cc decrement v cc reset pin goes active? measured v trip -desired v trip done execute sequence reset v trip set v cc = v cc applied = desired v trip execute sequence set v trip new v cc applied old v cc applied (v cc = v cc ?10mv) execute sequence reset v trip error -emax -emax < error < emax yes no error emax emax = maximum desired error - error = new v cc applied old v cc applied - error = figure 4. v trip programming sequence table 1. instruction set instruction name instruction format* operation wren 0000 0110 set the write enable latch (enable write operations) wrdi 0000 0100 reset the write enable latch (disable write operations) rsdr 0000 0101 read status register wrsr 0000 0001 write status register (watchdog and block lock) read 0000 a 8 011 read data from memory array beginning at selected address write 0000 a 8 010 write data to memory array beginning at selected address (1 to 16 bytes) x5043, x5045
9 fn8126.2 march 16, 2006 write enable latch the device contains a write enable latch. this latch must be set before a write operation is initiated. the wren instruction will set the latch and the wrdi instruction will reset the latch (figure 5). this latc h is automatically reset upon a power-up condition and after the completion of a valid byte, page, or status register write cycl e. the latch is also reset if wp is brought low. when issuing a wren, wrdi or rdsr commands, it is not necessary to send a byte address or data. status register the status register contains f our nonvolatile control bits and two volatile status bits. the co ntrol bits set the operation of the watchdog timer and the memory block lock protection. the status register is formatted as shown in ?status register?. the write-in-progress (wip) bit is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. the wip bit is read using the rdsr instruction. when set to a ?1?, a nonvolatile write operation is in progress. when set to a ?0?, no write is in progress. the write enable latch (wel) bit indicates the status of the ?write enable? latch. when we l = 1, the la tch is set and when wel = 0 the latch is rese t. the wel bit is a volatile, read only bit. the wren instruction sets the wel bit and the wrds instruction resets the wel bit. the block lock bits, bl0 and bl1, set the level of block lock protection. these nonvolatile bits are programmed using the wrsr instruction and allow the user to protect one quarter, one half, all or none of the eeprom array. any portion of the array that is block lock protected can be read but not written. it will remain protected until the bl bits are altered to disable block lock protection of that portion of memory. the watchdog timer bits, wd0 and wd1, select the watchdog time-out period. these nonvolatile bits are programmed with the wrsr instruction. read status register to read the status register, pull cs low to select the device, then send the 8-bit rdsr instruction. then the contents of the status register are shifted out on the so line, clocked by clk. refer to the read status register sequence (figure 6). the status register may be read at any time, even during a write cycle. write status register prior to any attempt to write data into the status register, the ?write enable? latch (wel) must be set by issuing the wren instruction (figure 5). first pull cs low, then clock the wren instruction into the device and pull cs high. then bring cs low again and enter the wrsr instruction followed by 8 bits of data. these 8 bits of data correspond to the contents of the status re gister. the operation ends with cs going high. if cs does not go high between wren and wrsr, the wrsr instruction is ignored. status register: (default = 30h) 7 6543210 00wd1wd0bl1bl0welwip 01234567 cs si sck high impedance so figure 5. write enable/disable latch sequence (wren/wrdi instruction) status reg bits array addresses protected bl1 bl0 x5043, x5045 0 0 none 0 1 $180?$1ff 1 0 $100?$1ff 1 1 $000?$1ff status register bits watchdog time out (typical) wd1 wd0 0 0 1.4 seconds 0 1 600 milliseconds 1 0 200 milliseconds 1 1 disabled (factory default) x5043, x5045
10 fn8126.2 march 16, 2006 table 2. device protect matrix wren cmd (wel) device pin (wp) memory block status register protected area unprotected area (bl0, bl1, wd0, wd1) 0 x protected protected protected x 0 protected protected protected 1 1 protected writable writable 01234567891011121314 76543210 data out cs sck si so msb high impedance instruction 15 figure 6. read status register sequence 0123456789 cs sck si so high impedance instruction data byte 765432 10 10 11 12 13 14 15 figure 7. write status register sequence x5043, x5045
11 fn8126.2 march 16, 2006 read memory array when reading from the eeprom memory array, cs is first pulled low to select the device. the 8-bit read instruction is transmitted to the device, followed by the 8-bit address. bit 3 of the read instruction selects the upper or lower half of the device. after the read opcode and address are sent, the data stored in the memory at the selected address is shifted out on the so line. the data st ored in memory at the next address can be read sequentially by continuing to provide clock pulses. the address is automatically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached, the address counter rolls over to address 000h allowing the read cycle to be continued indefinitely. the read operation is terminated by taking cs high. refer to the read eeprom array sequence (figure 8). write memory array prior to any attempt to write da ta into the memory array, the ?write enable? latch (wel) mu st be set by issuing the wren instruction (figure 5). first pull cs low, then clock the wren instruction into the device and pull cs high. then bring cs low again and enter the write instruction followed by the 8-bit address and then the data to be written. bit 3 of the write instruction contains address bit a 8 , which selects the upper or lower half of the array. if cs does not go high between wren and write, the write instruction is ignored. the write operation requires at least 16 clocks. cs must go low and remain low for the duration of the operation. the host may continue to write up to 16 bytes of data. the only restriction is that the 16 bytes must reside within the same page. a page address begins wi th address [x xxxx 0000] and ends with [x xxxx 1111]. if the byte address reaches the last byte on the page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that has been previously written. for the write operation (byte or page write) to be completed, cs must be brought high after bit 0 of the last complete data byte to be written is cloc ked in. if it is brought high at any other time, the write operation will not be completed (figure 9). while the write is in progress fo llowing a status register or memory array write sequence, the status register may be read to check the wip bit. wip is high while the nonvolatile write is in progress. 0 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 76543 210 data out cs sck si so msb high impedance instruction 8 bit address 76 5 3 210 8 9 th bit of address figure 8. read eeprom array sequence x5043, x5045
12 fn8126.2 march 16, 2006 operational notes the device powers-up in the following state: 1. the device is in the low power standby state. 2. a high to low transition on cs is required to enter an active state and receive an instruction. 3. so pin is high impedance. 4. the write enable latch is reset. 5. the flag bit is reset. 6. reset signal is active for t purst . data protection the following circuitry has been included to prevent inadvertent writes: ? a wren instruction must be issued to set the write enable latch. ?cs must come high at the proper clock count in order to start a nonvolatile write cycle. ? block protect bits provide additional level of write protection for the memory array. ?the wp pin low blocks nonvolatile write operations. 24 25 26 27 28 29 30 31 sck si cs 012345678910 sck si instruction 8 bit address data byte 1 76543210 cs 32 33 34 35 36 37 38 39 data byte 2 76543210 data byte 3 76543210 data byte n 765 3210 12 13 14 15 16 17 18 19 20 21 22 23 654 321 0 9 th bit of address 8 figure 9. write memory sequence x5043, x5045
13 fn8126.2 march 16, 2006 notes: 1. v il min. and v ih max. are for reference only and are not tested. 2. this parameter is periodically sampled and not 100% tested. 3. sck frequency measured from v cc x 0.1/v cc x 0.9 absolute maximum ratings recommended operating conditions temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65c to +135c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage on any pin with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to +7v d.c. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . 300c temperature: commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c supply voltage: -2.7, -2.7a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v blank, -4.5a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 5.5v caution: stresses above those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stres s rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating conditions for extend ed periods may affect device reliability. dc electrical specifications (over the recommended operating conditi ons unless otherwise specified.) symbol parameter test conditions/comments limits unit min typ (2) max i cc1 v cc write current (active) sck = 3.3mhz (3) ; so, reset , reset = open 3 ma i cc2 v cc read current (active) sck = 3.3mhz (3) ; si = v ss , reset , reset = open 2ma i sb1 v cc standby current wdt = off cs = v cc , sck, si = v ss , v cc =5.5v 10 a i sb2 v cc standby current wdt = on cs = v cc , sck, si = v ss , v cc =5.5v 50 a i li input leakage current sck, si, wp = v ss to v cc 0.1 10 a i lo output leakage current so, reset , reset = v ss to v cc 0.1 10 a v il (1) input low voltage sck, si, wp , cs -0.5 v cc x 0.3 v v ih (1) input high voltage sck, si, wp , cs v cc x 0.7 v cc + 0.5 v v ol output low voltage (so) i ol = 2ma @ v cc = 2.7v i ol = 0.5ma @ v cc = 1.8v 0.4 v v oh1 output high voltage (so) v cc > 3.3v, i oh = ?1.0ma v cc - 0.8 v v oh2 output high voltage (so) 2v < v cc 3.3v, i oh = ?0.4ma v cc - 0.4 v v oh3 output high voltage (so) v cc 2v, i oh = ?0.25ma v cc - 0.2 v v olrs output low voltage (reset , reset) i ol = 1ma 0.4 v capacitance t a = +25c, f = 1mhz, v cc = 5v symbol test conditions max unit c out (2) output capacitance (so, reset , reset) v out = 0v 8 pf c in (2) input capacitance (sck, si, cs , wp )v in = 0v 6 pf x5043, x5045
14 fn8126.2 march 16, 2006 equivalent a.c. load circuit at 5v v cc notes: 4. this parameter is periodically sampled and not 100% tested. 5. t wc is the time from the rising edge of cs after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. 5v output 30pf 5v 4.6k ? reset/reset 30pf 1.64k ? 1.64k ? a.c. test conditions input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 ac electrical specifications (over recommended operating conditi ons, unless otherwise specified) symbol parameter 2.7v?5.5v unit min max data input timing f sck clock frequency 0 3.3 mhz t cyc cycle time 300 ns t lead cs lead time 150 ns t lag cs lag time 150 ns t wh clock high time 130 ns t wl clock low time 130 ns t su data setup time 30 ns t h data hold time 30 ns t ri (4) input rise time 2s t fi (4) input fall time 2s t cs cs deselect time 100 ns t wc (5) write cycle time 10 ms data output timing symbol parameter 2.7?5.5v unit min max f sck clock frequency 0 3.3 mhz t dis output disable time 150 ns t v output valid from clock low 120 ns t ho output hold time 0 ns t ro (4) output rise time 50 ns t fo (4) output fall time 50 ns x5043, x5045
15 fn8126.2 march 16, 2006 serial output timing serial input timing symbol table sck cs so si msb out msb?1 out lsb out addr lsb in t cyc t v t ho t wl t wh t dis t lag sck cs si so msb in t su t ri t lag t lead t h lsb in t cs tfi high impedance waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance x5043, x5045
16 fn8126.2 march 16, 2006 power-up and power-down timing note: 6. this parameter is periodically sampled and not 100% tested. cs/wdi vs. reset/reset timing v cc t purst t f t rpd reset (x5043) 0 volts v trip reset (x5045) v trip t purst t r reset output timing symbol parameter min typ max unit v trip reset trip point voltage, (-4.5a) reset trip point voltage, (blank) reset trip point voltage, (-2.7a) reset trip point voltage, (-2.7) 4.5 4.25 2.85 2.55 4.62 4.38 2.92 2.62 4.75 4.5 3.0 2.7 v t purst power-up reset time out 100 200 400 ms t rpd (6) v cc detect to reset/output 500 ns t f (6) v cc fall time 10 s t r (6) v cc rise time 0.1 ns v rvalid reset valid v cc 1v cs /wdi t cst reset reset t wdo t rst t wdo t rst (5043) (5045) reset /reset output timing symbol parameter min typ max unit t wdo watchdog time out period, wd1 = 1, wd0 = 1 (default) wd1 = 1, wd0 = 0 wd1 = 0, wd0 = 1 wd1 = 0, wd0 = 0 100 450 1 off 200 600 1.4 300 800 2 ms ms sec t cst cs pulse width to reset the watchdog 400 ns t rst reset time out 100 200 400 ms x5043, x5045
17 fn8126.2 march 16, 2006 v trip programming timing diagram sck si cs 01h or v cc (v trip ) wp t tsu t thd t vph t vps v p v trip t rp t vpo t pcs 02h 06h 03h v trip programming parameters parameter description min max unit t vps v trip program enable voltage setup time 1 s t vph v trip program enable voltage hold time 1 s t pcs v trip programming cs inactive time 1 s t tsu v trip setup time 1s t thd v trip hold (stable) time 10 ms t wc v trip write cycle time 10 ms t vpo v trip program enable voltage off time (between successive adjustments) 0 s t rp v trip program recovery period (between successive adjustments) 10 ms v p programming voltage 15 18 v v tran v trip programmed voltage range 1.7 4.75 v v tv v trip program variation after programming (0-75c). (programmed at 25c.) -25 +25 mv v trip programming parameters are periodically sampled and are not 100% tested. x5043, x5045
18 fn8126.2 march 16, 2006 packaging information 0.118 0.002 (3.00 0.05) 0.040 0.002 (1.02 0.05) 0.150 (3.81) ref. 0.193 (4.90) 0.030 (0.76) 0.036 (0.91) 0.032 (0.81) 0.007 (0.18) 0.005 (0.13) 0.008 (0.20) 0.004 (0.10) 0.0216 (0.55) 7 typ. r 0.014 (0.36) 0.118 0.002 (3.00 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) typ. 8-lead miniature small outline gull wing package type m note: 1. all dimensions in inches and (millimeters) 0.220" 0.0256" typical 0.025" typical 0.020" typical 8 places footprint ref. x5043, x5045
19 fn8126.2 march 16, 2006 packaging information note: 1. all dimensions in inches (i n parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 8-lead plastic dual in-line package type p half shoulder width on all end pins optional .073 (1.84) max. 0.325 (8.25) 0.300 (7.62) plane x5043, x5045
20 fn8126.2 march 16, 2006 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 - 8 x 45 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050"typical 0.050" typical 0.030" typical 8 places footprint x5043, x5045
21 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8126.2 march 16, 2006 packaging information note: all dimensions in inches (in parentheses in millimeters) 14-lead plastic, tsso p, package type v see detail ?a? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 - 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) x5043, x5045
x5043 printer friendly version cpu supervisor with 4k spi eeprom datasheets, related docs & simulations description key features parametric data application diagrams related devices ordering information part no. design-in status temp. package msl price us $ x5043m8 active comm 8 ld msop 1 2.46 x5043m8-2.7 active comm 8 ld msop 1 2.46 x5043m8-2.7a active comm 8 ld msop 1 2.46 x5043m8-2.7at1 active comm 8 ld msop t+r 1 2.46 x5043m8-4.5a active comm 8 ld msop 1 2.46 x5043m8i active ind 8 ld msop 1 2.55 x5043m8i-2.7 active ind 8 ld msop 1 2.55 x5043m8i-2.7a active ind 8 ld msop 1 2.55 x5043m8i-2.7at1 active ind 8 ld msop t+r 1 2.55 x5043m8i-2.7t1 active ind 8 ld msop t+r 1 2.55 x5043m8i-2.7t2 active ind 8 ld msop t+r 1 2.55 x5043m8i-4.5a active ind 8 ld msop 1 2.55 x5043m8iz active ind 8 ld msop 2 2.55 x5043m8iz-2.7 active ind 8 ld msop 2 2.55 x5043m8iz-2.7a active ind 8 ld msop 2 2.55 x5043m8iz-2.7at1 active ind 8 ld msop t+r 2 2.55 x5043m8iz-2.7t1 active ind 8 ld msop t+r 2 2.55 x5043m8iz-4.5a active ind 8 ld msop 2 2.55 x5043m8z active comm 8 ld msop 2 2.46 x5043m8z-2.7 active comm 8 ld msop 2 2.46 x5043m8z-2.7a active comm 8 ld msop 2 2.46 x5043m8z-4.5a active comm 8 ld msop 2 2.46 x5043p active comm 8 ld pdip n/a 1.99 x5043p-2.7 active comm 8 ld pdip n/a 1.99 x5043p-2.7a active comm 8 ld pdip n/a 1.99 x5043p-4.5a active comm 8 ld pdip n/a 1.99 x5043pc1038 active comm 8 ld pdip n/a x5043pi active ind 8 ld pdip n/a 2.06 x5043pi-2.7 active ind 8 ld pdip n/a 2.06 x5043pi-2.7a active ind 8 ld pdip n/a 2.06 x5043pi-4.5a active ind 8 ld pdip n/a 2.06 x5043pi-4.5ac1038 active ind 8 ld pdip n/a x5043piz active ind 8 ld pdip n/a 2.06
x5043piz-2.7 active ind 8 ld pdip n/a 2.06 x5043piz-2.7a active ind 8 ld pdip n/a 2.06 x5043piz-4.5a active ind 8 ld pdip n/a 2.06 x5043pz active comm 8 ld pdip n/a 1.99 x5043pz-2.7 active comm 8 ld pdip n/a 1.99 x5043pz-2.7a active comm 8 ld pdip n/a 1.99 x5043pz-4.5a active comm 8 ld pdip n/a 1.99 x5043s8 active comm 8 ld soic 1 1.99 x5043s8-2.7 active comm 8 ld soic 1 1.99 x5043s8-2.7a active comm 8 ld soic 1 1.99 x5043s8-2.7at1 active comm 8 ld soic t+r 1 1.99 x5043s8-2.7t1 active comm 8 ld soic t+r 1 1.99 x5043s8-2.7t2 active comm 8 ld soic t+r 1 1.99 x5043s8-4.5a active comm 8 ld soic 1 1.99 x5043s8c1038 active comm 8 ld soic 1 x5043s8c7168 active comm 8 ld soic 1 x5043s8i active ind 8 ld soic 1 2.06 x5043s8i-2.7 active ind 8 ld soic 1 2.06 x5043s8i-2.7a active ind 8 ld soic 1 2.06 x5043s8i-2.7at1 active ind 8 ld soic t+r 1 2.06 x5043s8i-2.7t1 active ind 8 ld soic t+r 1 2.06 x5043s8i-2.7t2 active ind 8 ld soic t+r 1 2.06 x5043s8i-4.5a active ind 8 ld soic 1 2.06 x5043s8i-4.5at1 active ind 8 ld soic t+r 1 2.06 x5043s8it1 active ind 8 ld soic t+r 1 2.06 x5043s8it2 active ind 8 ld soic t+r 1 2.06 x5043s8it4 active ind 8 ld soic t+r 3 2.06 x5043s8iz active ind 8 ld soic 1 2.06 x5043s8iz-2.7 active ind 8 ld soic 1 2.06 x5043s8iz-2.7a active ind 8 ld soic 1 2.06 x5043s8iz-2.7at1 active ind 8 ld soic t+r 1 2.06 x5043s8iz-2.7t1 active ind 8 ld soic t+r 1 2.06 x5043s8iz-4.5a active ind 8 ld soic 1 2.06 x5043s8iz-4.5at1 active ind 8 ld soic t+r 1 2.06 x5043s8izt1 active ind 8 ld soic t+r 1 2.06 x5043s8izt2 active ind 8 ld soic t+r 1 2.06 x5043s8t1 active comm 8 ld soic t+r 1 1.99 x5043s8t2 active comm 8 ld soic t+r 1 1.99 x5043s8z active comm 8 ld soic 1 1.99 x5043s8z-2.7 active comm 8 ld soic 1 1.99 x5043s8z-2.7a active comm 8 ld soic 1 1.99 x5043s8z-2.7at1 active comm 8 ld soic t+r 1 1.99
x5043s8z-2.7t1 active comm 8 ld soic t+r 1 1.99 x5043s8z-4.5a active comm 8 ld soic 1 1.99 x5043s8zt1 active comm 8 ld soic t+r 1 1.99 x5043v14i active ind 14 ld tssop 1 2.55 x5043v14i-2.7 active ind 14 ld tssop 1 2.55 x5043v14i-2.7a active ind 14 ld tssop 1 2.55 x5043v14i-4.5a active ind 14 ld tssop 1 2.55 x5043v14iz active ind 14 ld tssop 1 2.55 x5043v14iz-2.7 coming soon ind 14 ld tssop 1 x5043v14iz-2.7a coming soon ind 14 ld tssop 1 x5043v14iz-4.5a coming soon ind 14 ld tssop 1 the price listed is the manufacturer's suggested retail price for quantities between 100 and 999 units. however, prices in today's market are fluid and may change without notice. msl = moisture sensitivity level - per ipc/jedec j-std-020 smd = standard microcircuit drawing description these devices combine four popular functions, poweron reset control, watchdog timer, supply voltage supervision, and block lock protect serial eeprom memory in one package. this combination lowers system cost, reduces board space requirements, and increases reliability. applying power to the device activates the power-on reset circuit which holds reset /reset active for a period of time. this allows the power supply and oscillator to stabilize before the processor executes code. the watchdog timer provides an independent protection mechanism for microcontrollers. when the microcontroller fails to restart a timer within a selectable time out interval, the device activates the reset /reset signal. the user selects the interval from three preset values. once selected, the interval does not change, even after cycling the power. the device?s low v cc detection circuitry protects the user?s system from low voltage conditions, resetting the system when v cc falls below the minimum v cc trip point. reset /reset is asserted until v cc returns to proper operating level and stabilizes. four industry standard v trip thresholds are available, however, intersil?s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. the memory portion of the device is a cmos serial eeprom array with intersil?s block lock protection. the array is internally organized as 512 x 8. the device features a serial peripheral interface (spi) and software protocol allowing operation on a simple fourwire bus. the device utilizes intersil?s proprietary direct write? cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. key f eatures low v cc detection and reset assertion four standard reset threshold voltages 4.63v, 4.38v, 2.93v, 2.63v re-program low v cc reset threshold voltage using special programming sequence. reset signal valid to v cc = 1v selectable time out watchdog timer long battery life with low power consumption <50a max standby current, watchdog on <10a max standby current, watchdog off 4kbits of eeprom?1m write cycle endurance save critical data with block lock? memory protect 1/4, 1/2, all or none of eeprom array built-in inadvertent write protection write enable latch write protect pin spi interface - 3.3mhz clock rate minimize programming time 16-byte page write mode
5ms write cycle time (typical) available packages 8 ld msop, 8 ld soic, 8 ld pdip 14 ld tssop pb-free plus anneal available (rohs compliant) related documentation application note(s): designing with intersil?s x5000 series cpu supervisors interfacing the x5043 watchdog timer to hitachi h8/3000 microcontrollers x5043, x5045 system supervisors manage 8051 type microcontrollers datasheet(s): cpu supervisor with 4k spi eeprom parametric data number of voltage monitors 1 v s range (v) 4.5 to 5.5 4.5 to 5.5 2.7 to 5.5 2.7 to 5.5 voltage threshold 1 4.62 (2.6%) 4.38 (3%) 2.92 (2.4%) 2.62 (2.7%) reset output type active high watchdog timer (s) off, 0.2, 0.6, 1.4 manual reset n bus interface spi eeprom size (kbits) 4 battery montor and switchover n fault detection register n suffix -4.5a blank -2.7a -2.7 por (ms) y rtc function n application block diagrams frame grabber applications communications equipment routers, hubs, switches set top boxes industrial systems process control intelligent instrumentation computer systems desktop computers network servers battery powered equipment related devices parametric table
x5001 cpu supervisor x5045 cpu supervisor with 4k spi eeprom x5083 cpu supervisor with 8kbit spi eeprom x5163 cpu supervisor with 16kbit spi eeprom x5165 cpu supervisor with 16kbit spi eeprom x5168 cpu supervisor with 16kbit spi eeprom x5169 cpu supervisor with 16kbit spi eeprom x5323 cpu supervisor with 32kb spi eeprom x5325 cpu supervisor with 32kb spi eeprom x5328 cpu supervisor with 32kbit spi eeprom x5329 cpu supervisor with 32kbit spi eeprom about us | careers | contact us | investors | legal | privacy | site map | subscribe | intranet ?2007. all rights reserved.

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